1. Field of the Invention
Embodiments of the invention relate to adapting level sensitive devices for use in edge triggered systems. In particular, embodiments of the invention relate to adapting level sensitive random access memory devices for use with built in self test systems designed for use with edge triggered devices.
2. Background
Many computers systems are being designed to improve the level of system reliability by including built in self test (BIST) software and hardware modules that check the operating condition of the components that comprise the computer system. The BIST alerts the system to faulty hardware components or sub components and allows the computer system to avoid using these components or notify a user of their condition if they fail during testing in order to avoid catastrophic failures and increase up-time and reliability of the system.
Many BIST modules were designed to test edge triggered devices. An edge triggered device produces reliable outputs at a predefined period after the leading edge of a clock signal. An edge triggered register file or memory module if presented with a read request on a first clock edge will usually produce the requested data by the leading edge of the next clock cycle. Level sensitive devices include latches, and certain types of memory caches and random access memory (RAM) modules such as static RAMs (SRAMs). Level sensitive devices are driven by voltage levels of incoming signals including clock signals. For example, a level sensitive SRAM which receives a typical square wave clock signal when starting a read operation may have a ‘high’ output for the period when the clock signal is high. Data is output during the ‘low’ phase of the clock signal and when the clock signal again transitions to a ‘high’ level, the data output also begins to transition.
BIST modules typically are designed to test edge triggered devices. Edge triggered devices allow output changes to occur based only on input at a single clocked instant which is an edge of a clock signal. The output is stable at a predefined period after that same clock edge. Many BIST modules expect edge triggered device behavior such as stable and deterministic output at a clock edge. Thus, BIST modules cannot accurately test level-sensitive devices. BIST modules test memory devices by sending a read request to a device to be tested after having stored a known value at a given address location in the device. The read request retrieves the stored value and sends it back to the BIST module for verification. The read request occurs on a first leading clock edge. Output is expected on the next leading clock edge. However, the output for a level sensitive device (with “transparent” pre-charge) will begin to transition to a high output when it receives the next leading clock edge causing a non-deterministic value to be read by the BIST module on the second leading clock edge.